MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 169

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.15.4.9 Floating-Point Unavailable Interrupt
3.15.4.10 Trace Interrupt
3.15.4.11 Floating-Point Assist Interrupt
MPC555
USER’S MANUAL
The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core
as defined in the OEA.
A trace interrupt occurs if MSR
pleted or MSR
not occur after an instruction that caused an interrupt (for instance, sc). A monitor/de-
bugger software must change the vectors of other possible interrupt addresses to sin-
gle-step such instructions. If this is unacceptable, other debug features can be used.
Refer to
ing registers are set:
Execution resumes at offset 0x00D00 from the base address indicated by MSR
A floating-point assist interrupt occurs in the following cases:
The following registers are set:
Execution resumes at offset 0x00E00 from the base address indicated by MSR
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• When a floating-point exception condition is detected, the corresponding floating-
• When an intermediate result is detected and the floating-point underflow excep-
• In some cases when at least one of the source operands is denormalized.
/
point enable bit in the FPSCR (floating-point status and control register) is set (ex-
ception enabled) and ((MSR
MSR
rfi, the floating-point assist interrupt handler is not invoked.
tion is disabled (FPSCR
MPC556
Register Name
SECTION 21 DEVELOPMENT SUPPORT
FE1
) and FPSCR
BE
= 1 and a branch is completed. Notice that the trace interrupt does
Freescale Semiconductor, Inc.
For More Information On This Product,
FEX
CENTRAL PROCESSING UNIT
10:15
Other
Other
UE
Bits
ME
Go to: www.freescale.com
1:4
LE
IP
SE
) is set as a result of move to FPSCR, move to MSR or
Rev. 15 October 2000
= 0)
= 1 and any instruction except rfi is successfully com-
FE0
Bit is copied from ILE
Set to 0
Set to the effective address of the instruction following the ex-
ecuted instruction
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
| MSR
FE1
) = 1). Note that when ((MSR
RI
for more information. The follow-
Description
MOTOROLA
IP.
IP
FE0
.
3-47
|