MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 183

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
n+1
(n) and (n+1) are word addresses in the original uncompressed code
n
n+1
n
The compiler will set the left and right stream boundary at either bit 12 or bit 19. This
will be determined by the most efficient placement of compressed instruction code.
The boundary will be placed between bits 11 and 12 if bit 31 is equal to one. The
boundary will be placed between bits 18 and 19 if bit 31 is equal to zero. The original
right and left streams may span an adjacent base addresses before or after each oth-
er. This fact will also determine the placement of the boundary bit field.
Each stream line may include a variable number of compressed symbols, depending
on how well the bytes in the original stream were compressed.
The decompressor has to maintain two bit pointers (left and right) in order to have ac-
cess to the start location of any instruction’s half.
The decompressor maintains tracking of the base address, to start fetching from the
next address in the memory.
Xn,1
/
Uncompressed Code
0
0
MPC556
Figure 4-6 Examples of Compressed Symbols Layout
Xn,2
Freescale Semiconductor, Inc.
For More Information On This Product,
8
8
Xn+1,1
Go to: www.freescale.com
Rev. 15 October 2000
BURST BUFFER
Boundary assumed to be 12 for both lines
15
15
Compressed Code Stream
0
0
MOTOROLA
11
11
4-7