MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 215

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
SGPIOD[16:23]
SGPIOD[24:31]
SGPIOA[16:23]
SGPIOA[24:31]
NOTES:
SGPIOD[8:15]
SGPIOA[8:15]
SGPIOC[0:7]
Group Name
SGPIOD[0:7]
tionality. The functionality of these pins is assigned by the single-chip (SC) bit in the
SIUMCR. (See
SGPIO pins are grouped as follows:
Table 6-2
registers are described in
1. SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See
SGPIO
ration
• Six groups of eight pins each, whose direction is set uniformly for the whole group
• 16 single pins whose direction is set separately for each pin
Figure 6-3
/
MPC556
Register.
1
describes the SGPIO signals, and all available configurations. The SGPIO
Pin Control
Individual
illustrates the functionality of the SGPIO.
6.13.1.1 SIU Module Configuration
X
X
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
For More Information On This Product,
SDDRD[23:31]
Table 6-2 SGPIO Configuration
SDDRC[0:7]
Direction
Control
6.13.5 General-Purpose I/O
GDDR0
GDDR1
GDDR2
GDDR3
GDDR4
GDDR5
Go to: www.freescale.com
Rev. 15 October 2000
When SC = 00
(32-bit Port
Size Mode)
Available
When SC = 01
(16-bit Port
Size Mode)
Available
Register.)
X
X
Registers.
When SC = 10
(Single-Chip
6.13.1.1 SIU Module Configu-
Mode with
Available
Trace)
X
X
X
X
When SC = 11
(Single-Chip
MOTOROLA
Available
Mode)
X
X
X
X
X
X
X
6-7