MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 250

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Power On Reset
Hard Reset Sources
External Hard Reset
Loss of Lock
On-Chip Clock Switch
Illegal Low-Power Mode
Software Watchdog
Checkstop
Debug Port Hard Reset
Soft Reset Sources
External Soft Reset
Debug Port Soft Reset
JTAG Reset
7.3 Data Coherency During Reset
MPC555
USER’S MANUAL
HRESET
SRESET
HRESET & SRESET
The MPC555 / MPC556 supports data coherency and avoids data corruption while re-
set. If a cycle is to be executed when detecting any SRESET or HRESET source, then
the cycle will either complete or will not start before generating the corresponding reset
control signal. There are reset sources, however, when the MPC555 / MPC556 gen-
erates an internal reset due to special internal situation where this protection is not
supported. See
In the case of large operand size (32 or 16 bits) transaction to a smaller port size, the
cycle is split into two 16-bit or four 8-bit cycles. In this case, data coherency is assured
and data will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken
down into multiple cycles, data coherency is NOT assured between these cycles (i.e.,
data could be corrupted).
A contention on the data pins may occur while asserting external reset (EXT_RESET)
if the data coherency mechanism is required, and thus enables a cycle to complete,
while external hardware drives the data for the configuration word. See
a description of the required EXT_RESET line source in a system.
Reset Source
Table 7-2 Reset Configuration Word and Data Corruption/Coherency
/
MPC556
Reset Driven
Table 7-1 Reset Action Taken For Each Reset Cause
7.4 Reset Status
Logic and
Freescale Semiconductor, Inc.
States
Reset
Reset
PLL
Yes
No
No
For More Information On This Product,
SRESET
HRESET
HRESET || SRESET
Reset to Use for Data Coherency
Configura-
tion Reset
System
Go to: www.freescale.com
Yes
Yes
Rev. 15 October 2000
No
Register.
(EXT_RESET)
RESET
Module
Clock
Reset
Yes
Yes
No
Pin Driven
HRESET
Yes
Yes
No
Provided only one of them is driven
into the MPC555 / MPC556 at a time
Configura-
Debug
Port
tion
Yes
Yes
Yes
Comments
Internal
Reset
Other
Logic
Yes
Yes
Yes
Table 7-2
MOTOROLA
Pin Driven
SRESET
Yes
Yes
Yes
for
7-4