MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 265

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.3.5 PLL Pins
MPC555
USER’S MANUAL
OSCCLK
The PLL maximum lock time is determined by the input clock to the phase detector.
The PLL locks within 500 input clock cycles.
Whenever power-on reset is asserted, the MF bits are set according to
the DFNH and DFNL bits in SCCR are set to the value of 0 (÷1 and 2), respectively.
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the V
• VSSSYN — Source voltage. This is the V
• XFC — External filter capacitor. XFC connects to the off-chip capacitor for the
/
The voltage should be well-regulated and the pin should be provided with an ex-
tremely low impedance path to the V
to VSSSYN by a 0.1 µF capacitor located as close as possible to the chip pack-
age.
The pin should be provided with an extremely low impedance path to ground.
VSSSYN should be bypassed to VDDSYN by a 0.1 µF capacitor located as close
as possible to the chip package.
PLL filter. One terminal of the capacitor is connected to XFC, and the other termi-
nal is connected to VDDSYN.
The off-chip capacitor must have the following values:
MPC556
Division Factor
Upon initial system power up and after KAPWR is lost, an external
circuit must assert power on reset (PORESET). If limp mode will be
enabled during power-on reset, PORESET must be asserted for at
least 100,000 cycles of input PLL clock after a valid level has been
reached on the KAPWR supply. If limp mode will be disabled,
PORESET should be asserted for approximately 3 µs after a valid
level has been reached on the KAPWR supply.
DIVF[0:4]
Feedback
Freescale Semiconductor, Inc.
Figure 8-3 System PLL Block Diagram
For More Information On This Product,
CLOCKS AND POWER CONTROL
Comparator
Phase
Go to: www.freescale.com
Rev. 15 October 2000
Clock
Delay
Down
Up
DD
NOTE
power rail. VDDSYN should be bypassed
DD
SS
Charge
Pump
dedicated to the analog PLL circuits.
dedicated to the analog PLL circuits.
VDDSYN / VSSSYN
Multiplication Factor
XFC
MF[0:11]
VCO
Table
(FREQ
System
Frequency
MOTOROLA
÷2
8-1, and
SYS
÷2
)
8-5