MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 270

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
VCO/2 (e.g., 40 MHz)
2 = 20 MHz (assuming a 20-MHz system frequency) with default power-on reset MF
values.
The general system clock frequency can be switched between different values. The
highest operational frequency can be achieved when the system clock frequency is
determined by DFNH (CSRC bit in the PLPRCR is cleared) and DFNH = 0 (division by
one). The general system clock can be operated at a low frequency (gear mode) or a
high frequency. The DFNL bits in SCCR define the low frequency. The DFNH bits in
SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the sys-
tem clock control register (SCCR), as shown in
The frequency of the general system clock can be changed “on the fly” by software.
The user may simply cause the general system clock to switch to its low frequency.
However, in some applications, there is a need for a high frequency during certain pe-
riods. Interrupt routines, for example, may require more performance than the low fre-
quency operation provides, but must consume less power than in maximum frequency
operation. The MPC555 / MPC556 provides a method to automatically switch between
low and high frequency operation whenever one of the following conditions exists:
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the gen-
eral system clock switches automatically back to the low frequency.
Abrupt changes in the divide ratio can cause linear changes in the operating currents
of the MPC555 / MPC556. Insure that the proper power supply filtering is available to
handle this change instantaneously.
When the general system clock is divided, its duty cycle is changed. One phase re-
mains the same (e.g., 12.5 ns @ 40 MHZ) while the other become longer. Note that
CLKOUT does not have a 50% duty cycle when the general system clock is divided.
The CLKOUT waveform is the same as that of GCLK2_50.
• There is a pending interrupt from the interrupt controller. This option is maskable
• The (POW) bit in the MSR is clear in normal operation. This option is maskable
O
/
by the PRQEN bit in the SCCR.
by the PRQEN bit in the SCCR.
MPC556
Figure 8-5 General System Clocks Select
Freescale Semiconductor, Inc.
For More Information On This Product,
DFNH Divider
DFNL Divider
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
Rev. 15 October 2000
DFNH
DFNL
Figure
8-5.
O
O
Normal
Low Power
O
General System Clock
MOTOROLA
8-10