MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 272

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.6.2 CLKOUT
8.6.3 Engineering Clock
MPC555
USER’S MANUAL
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike
the main system clock GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) repre-
sents the external bus clock, and thus will be one-half of the main system clock if the
external bus is running at half speed (EBDF = 0b01). The CLKOUT frequency defaults
to VCO/2. CLKOUT can drive full- or half-strength or be disabled. The drive strength
is controlled in the system clock and reset-control register (SCCR). Disabling or de-
creasing the strength of CLKOUT can reduce power consumption, noise, and electro-
magnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low
state (provided that BUCS = 0).
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128
which is one-sixtyfourth of the main system frequency. ENGCLK frequency can be pro-
grammed to the main system frequency divided by a factor from one to 64, as con-
trolled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can drive full- or half-strength
or be disabled (remaining in the high state). The drive strength is controlled by the EE-
CLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption, noise,
and electromagnetic interference on the printed circuit board.
1.
Mask sets prior to K62N default to VCO/4.
/
MPC556
Figure 8-7 Clocks Timing For DFNH = 1 (or DFNL = 0)
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
8-12
1
,