MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 313

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
and asserts or negates the BDIP signal. If the master does not intend to drive another
data beat following the current one, it negates BDIP to indicate to the slave that the
next data beat transfer is the last data of the burst write transfer.
BDIP has two basic timings: normal and late (see
late timing mode, assertion of BDIP is delayed by the number of wait states in the first
data beat. This implies that for zero-wait-state cycles, BDIP assertion time is identical
in normal and late modes. Cycles with late BDIP generation can occur only during cy-
cles for which the memory controller generates TA internally. Refer to
MEMORY CONTROLLER
In the MPC555 / MPC556, no internal master initiates write bursts. The MPC555 /
MPC556 is designed to perform this kind of transaction in order to support an external
master that is using the memory controller services. Refer to
External Master
During the data phase of a burst read cycle, the master receives data from the ad-
dressed slave. If the master needs more than one data beat, it asserts BDIP. Upon
receiving the second-to-last data beat, the master negates BDIP. The slave stops driv-
ing new data after it receives the negation of the BDIP signal at the rising edge of the
clock.
/
MPC556
Support.
Freescale Semiconductor, Inc.
For More Information On This Product,
for more information.
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
Figure 9-13
10.7 Memory Controller
and
Figure
SECTION 10
9-14). In the
MOTOROLA
9-17