MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 329

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.6.4 Internal Bus Arbiter
MPC555
USER’S MANUAL
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR & Attr.
TS
TA
The MPC555 / MPC556 can be configured at system reset to use the internal bus ar-
biter. In this case, the MPC555 / MPC556 will be parked on the bus. The parking fea-
ture allows the MPC555 / MPC556 to skip the bus request phase, and if BB is negated,
assert BB and initiate the transaction without waiting for BG from the arbiter.
The priority of the external device relative to the internal MPC555 / MPC556 bus mas-
ters is programmed in the SIU module configuration register. If the external device re-
quests the bus and the MPC555 / MPC556 does not require it, or if the external device
has higher priority than the current internal bus master, the MPC555 / MPC556 grants
the bus to the external device.
Table 9-4
/
MPC556
describes the priority mechanism used by the internal arbiter.
Figure 9-25 Bus Arbitration Timing Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
“Turns On” and
Drives Signals
Master 0
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
(Three-state Controls)
and “Turns Off”
Negates BB
Master 0
“Turns On” and
Drives Signals
Master 1
MOTOROLA
9-33