MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 337

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
The reservation protocol for a single-level (local) bus is illustrated in
protocol assumes that an external logic on the bus carries out the following functions:
The MPC555 / MPC556 samples the CR line at the rising edge of CLKOUT. When this
signal is asserted, the reservation flag is reset.
The EBI samples the logical value of the reservation flag prior to externally starting a
bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI
begins with the bus cycle. If the reservation flag is reset, no bus cycle is initiated ex-
ternally, and this situation is reported to the RCPU.
The reservation protocol for a multi-level (local) bus is illustrated in
system describes the situation in which the reserved location is sited in the remote
bus.
lwarx
• Snoops accesses to all local bus slaves
• Holds one reservation for each local master capable of storage reservations
• Sets the reservation when that master issues a load and reserve request
• Clears the reservation when some other master issues a store to the reservation
/
address
MPC556
MPC555 /
MPC556
External Bus
CLKOUT
S
R
Interface
Q
Freescale Semiconductor, Inc.
Figure 9-29 Reservation On Local Bus
For More Information On This Product,
AT[0:3], RSV, R/W, TS
EXTERNAL BUS INTERFACE
CR
Go to: www.freescale.com
Rev. 15 October 2000
External Bus
Reservation
Logic
ADDR[0:29]
CR
Figure
Figure
MOTOROLA
9-30. The
9-29. The
Master
Bus
9-41