MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 359

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.3.1 Memory Devices Interface Example
MPC555
USER’S MANUAL
wait states counter has expired, this assertion terminates the memory cycle. When
SETA is cleared, it is forbidden to assert external TA less than two clocks before the
wait states counter expires.
Figure 10-5
static memory device. In this case CSx is connected directly to the chip enable (CE)
of the memory device. The WE/BE[0:3] lines are connected to the respective W in the
memory device where each WE/BE line corresponds to a different data byte.
In
strobes for the transaction are supplied by the OE and the WE/BE lines (if pro-
grammed as WE/BE). Because the ACS bits in the corresponding ORx register = 00,
CS is asserted at the same time that the address lines are valid. Note that because
CSNT is set, the WE signal is negated a quarter of a clock earlier than normal.
Figure
/
MPC556
Figure 10-5 MPC555 / MPC556 GPCM–Memory Devices Interface
10-6, the CSx timing is the same as that of the address lines output. The
MPC555 / MPC556
describes the basic connection between the MPC555 / MPC556 and a
Freescale Semiconductor, Inc.
Address
WE/BE
For More Information On This Product,
Data
CSx
OE
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
Address
CE
OE
W
Data
Memory
MOTOROLA
10-7