MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 371

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
TRLX
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
NOTE: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-
Additional timing rules not covered in
case timing values. 1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if
• If TRLX = 1, the number of wait states = 2 * SCY & 2 * BSCY
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a
• If LBDIP = 1 (late BDIP assertion), the BDIP pin is asserted only after the number
Access
/
SCY = 0000)
following read cycle to another region, or between a read cycle and a following
write cycle to any region.
of wait states for the first beat in a burst have elapsed. See
TION 9 EXTERNAL BUS INTERFACE
that this function can operate only when the cycle termination is internal, using the
number of wait states programmed in one of the ORx registers
Read
Read
Read
Read
Read
Read
Type
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
MPC556
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
Table 10-2 Programming Rules for Strobes Timing
CSNT
X
X
X
X
X
X
0
0
0
1
1
1
0
0
0
1
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
1/4 * clock
1/2 * clock
1/4 * clock
1/2 * clock
1/4 * clock
1/2 * clock
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
Asserted
Address
to CS
clock
clock
clock
clock
clock
clock
0
0
0
0
0
0
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/2 * clock
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
Invalid
clock
clock
CS
Table 10-2
as well as
Address to
WE/BE or
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
(1 + 3/4) *
(1 + 3/4) *
(1 + 3/4) *
Asserted
3/4 clock
3/4 clock
3/4 clock
(1 + 3/4)
(1 + 3/4)
(1 + 3/4)
clock
clock
clock
clock
clock
clock
OE
include the following:
9.5.4 Burst
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/2 * clock
1/2 * clock
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
(1 + 1/2) *
WE/BE
Invalid
clock
clock
clock
X
X
X
X
X
X
Figure 9-13
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
Mechanism. Note
Invalid
OE
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA
Number of
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
Cycles
in
Total
2 +
3 +
3 +
2 +
3 +
3 +
3 +
4 +
4 +
SEC-
10-19