MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 374

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Note that dual mapping can operate only for addresses within the FLASH pre-allocat-
ed address (up to 2 Mbytes). This is achieved by programming only six bits for the
base address (11:16); The upper bits are always set as follows:
Where ISB[0:2] represents the bit field in IMMR register that determines the location
of the address map of the MPC555 / MPC556.
With dual mapping, aliasing of address spaces may occur. This happens when the
user maps the dual-mapped region into a region which is also mapped into one of the
four regions available in the memory controller. If the user writes code or data to the
dual-mapped region, care must be taken to avoid overwriting this code or data by nor-
mal accesses of the chip-select region.
There is a match if:
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped
code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only
the dual-mapped region (DME = 1, but Vx = 0, where x = selected region, 0.3).
10-17
• The memory controller takes control of the external access
• The attributes for the access are taken from one of the base and option registers
• The chip-select region selected is determined by the “CS line select” bit field
/
of the appropriate chip select
(10.8.5 Dual Mapping Base Register
MPC556
illustrates the phenomena.
bus_address[0:16] == {0000000,isb[0:2],0,dmbr_reg_value[1:6]}
Freescale Semiconductor, Inc.
For More Information On This Product,
bus_addr[0:10]={0000000,isb[0:2],0}
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
(DMBR)).
MOTOROLA
Figure
10-22