MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 383

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.8.5 Dual Mapping Base Register (DMBR)
MPC555
USER’S MANUAL
DMBR — Dual Mapping Base Register
HARD RESET:
Bit(s)
24:27
28:30
MSB
16
23
31
0
0
0
0
*The reset value is a reset configuration word value extracted from the indicated internal data bus lines.
HARD RESET:
17
U
/
1
0
MPC556
Name
EHTR
BSCY
TRLX
SCY
18
U
2
0
Table 10-8 OR0 – OR3 Bit Descriptions (Continued)
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a
read access from the current bank and any MPC555 / MPC556 write accesses or read accesses
to a different bank.
0 = Memory controller generates normal timing
1 = Memory controller generates extended hold timing
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining
the length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If the user has selected an external TA response for this memory bank (by setting the SETA bit),
then the SCY field is not used.
NOTE: Following a system reset, the SCY bits are set to 0b1111 in OR0.
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus us-
ing SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is is (1 + BSCY) x Clocks.
If the user has selected an external TA response for this memory bank (by setting the SETA bit)
then BSCY[0:3] are not used.
000 = 0-clock-cycle (1 clock per data beat)
001 = 1-clock-cycle wait states (2 clocks per data beat)
010 = 2-clock-cycle wait states (3 clocks per data beat)
011 = 3-clock-cycle wait states (4 clocks per data beat)
1xx = Reserved
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory de-
vices during a memory access to this memory region. Relaxed timing multiplies by two the num-
ber of wait states determined by the SCY and BSCY fields. Refer to
Timing Options
0 = Normal timing is generated by the GPCM.
1 = Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
19
U
3
0
BA
Freescale Semiconductor, Inc.
20
U
4
0
For More Information On This Product,
RESERVED
21
for a full list of the effects of this bit on pins timing.
U
5
0
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
22
U
6
0
23
7
0
0
RESERVED
,
24
8
0
0
Description
25
9
0
0
10
26
0
0
AT
11
27
0
0
10.3.5 Summary of GPCM
12
28
1
0
DMCS
13
29
0
0
RESERVED
0x2F C140
MOTOROLA
14
30
0
0
ID31*
DME
10-31
LSB
15
31
0