MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 389

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.4.1 Normal Mode
11.4.2 Reset Operation
11.4.3 Factory Test Mode
11.4.4 Peripheral Mode
MPC555
USER’S MANUAL
In normal mode (master or slave) the L2U module acts as a bi-directional protocol
translator. In master mode the CPU is fully operational, and there is no external master
access to the U-bus. Slave mode enables an external master to access any internal
bus slave while the CPU is fully operational. The L2U transfers load/store accesses
from the RCPU to the U-bus and the read/write accesses by the U-bus master to the
L-bus.
In addition to the bus protocol translation, the L2U supports other functions such as
show cycles, data memory protection and PowerPC reservation protocol.
When a load from the U-bus resource or store to the U-bus resource is issued by the
RCPU, it is compared against the DMPU region access (address and attribute) com-
parators. If none of the access attributes are violated, the access is directed to the U-
bus by the L2U module. If the DMPU detects an access violation, it informs the error
status to the master initiating the cycle.
When show cycles are enabled, accesses to all of the L-bus resources by the RCPU
are made visible on the U-bus side by the L2U.
The L2U is responsible for handling the effects of reservations on the L-bus and
the U-bus. For the L-bus and the U-bus, the L2U detects reservation losses and up-
dates the RCPU core with the reservation status.
Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are
ignored. The L2U module control registers are not initialized on the assertion of a soft
reset, keeping the system configuration unchanged.
Upon assertion of hard reset, the L2U control registers are initialized to their reset
states.
While reset (hard or soft) is asserted on the U-bus, the L2U asserts the corresponding
L-bus reset signals. The L2U also drives the reset configuration word from the U-bus
to the L-bus upon assertion of hard reset.
Factory test mode is a special mode of operation that allows access to the internal
modules for testing. This mode is not intended for general use and is not supported for
normal applications.
In the peripheral mode of operation the RCPU is shut down and an alternative master
on the external bus can perform accesses to any internal bus (U-bus and L-bus) slave.
The external master can also access the internal PowerPC special registers that are
located in L2U. In order to access one of these PowerPC registers the EMCR[CONT]
bit in the USIU must be cleared.
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
11-3