MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 396

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.7.3 Show Cycle Protocol
11.7.4 L-Bus Write Show Cycle Flow
MPC555
USER’S MANUAL
processed, and not lose an L-bus access that would have been show cycled, the L2U
module will arbitrate for the L-bus whenever it is processing any access. This L-bus
arbitration will prevent any other L-bus master from starting a cycle that might turn out
to be a qualifiable L-bus show cycle.
For L-bus show cycles, the minimum performance impact on the L-bus will be three
clocks. This minimum impact assumes that the L-bus slave access is a 1-clock access,
and the L2U module acquires immediate bus grant on the U-bus. The L2U has to wait
two clocks before completing the show cycle on the U-Bus, thus using up five clocks
for the complete process.
A retried access on the L-bus (no address acknowledge) that qualifies to be show cy-
cled, will be accepted when it is actually acknowledged. This will cause a 1-clock delay
before an L-bus master can retry the access on the L-bus, because the L2U module
will release L-bus one clock later.
L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks
when starting a show cycle on the U-bus.
The L2U module behaves as both a master and a slave on the U-bus during show cy-
cles. The L2U starts the U-bus transfer as a a bus master and then completes the ad-
dress phase and data phase of the cycle as a slave. The L2U follows U-bus protocol
of in-order termination of the data phase.
The USIU can control the start of show cycles on the U-bus by asserting the no-show
cycle indicator. This will cause the L2U module to release the U-bus for at least one
clock before retrying the show cycle.
The L2U performs the following sequence of actions for an L-bus-write show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting
2. Latches the address and the data of the L-bus access, along with all address
3. Waits for the termination of the L-bus access and latches the termination status
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting
5. When the L2U module has U-bus data bus grant, it drives the data phase ter-
6. Releases the L-bus
/
MPC556
attributes
(data error)
show cycle request on the U-bus, along with address, attributes and the write
data. The L2U module provides address recognize and acknowledgment for
the address phase. If the no-show cycle indicator from the U-bus is asserted,
the L2U does not start the show cycle. The L2U module releases the U-bus until
the no-show cycle indicator is negated and then arbitrates for the U-bus again.
mination handshakes on the U-bus.
Freescale Semiconductor, Inc.
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
11-10