MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 424

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.9.1 Conversion Cycle Times
MPC555
USER’S MANUAL
VSSA
VDDA
PQA7
PQA0
PQB7
PQB0
VRH
VRL
Total conversion time is made up of initial sample time, final sample time, and resolu-
tion time. Initial sample time refers to the time during which the selected input channel
is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be
disabled by means of the BYP bit in the CCW. During the final sampling period, ampli-
fier is bypassed, and the multiplexer input charges the RC DAC array directly. During
the resolution period, the voltage in the RC DAC array is converted to a digital value
and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is
ten QCLK cycles.
Sample and resolution require a minimum of 14 QCLK clocks (7 µs with a 2-MHz
QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total
conversion time is 13.0 µs with a 2-MHz QCLK.
Figure 13-5
sampling period of two QCLK cycles.
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
ANALOG
POWER
10 BIT A/D CONVERTER
illustrates the timing for conversions. This diagram assumes a final
10 BIT RC
DAC
Figure 13-4 QADC64 Module Block Diagram
Freescale Semiconductor, Inc.
COMPAR-
CHAN. DECODE & MUX
For More Information On This Product,
ATOR
SAMPLE
BUFFER
16: 1
Go to: www.freescale.com
INPUT
CSAMP
Rev. 15 October 2000
APPROXIMATION
6
SUCCESSIVE
STATE MACHINE & LOGIC
REGISTER
10
SAR Timing
BIAS CIRCUIT
CHAN.[5:0]
10
POWER
DOWN
2
SAR
CCW
BUF
BUF
10
10
STOP
RST
QCLK
WCCW
END OF CONV.
END OF SMP
CCW
SAR
QADC64 DETAIL BLOCK
MOTOROLA
RSAR
13-12