MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 427

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.10.1 Queue Priority
MPC555
USER’S MANUAL
occur for Queue 1 and Queue 2
Queue 1 active/trigger event
Queue 2 active/trigger event
Simultaneous trigger events
be created within the two queues. Each queue can be operated using several different
scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1
and QACR2. Once a queue has been started by a trigger event (any of the ways to
cause the QADC64 to begin executing the CCWs in a queue or sub-queue), the
QADC64 performs a sequence of conversions and places the results in the result word
table.
Queue 1 has execution priority over queue 2 execution.
tions under which queue 1 asserts its priority:
Figure 13-7
queues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two
CCWs in each sub-queue.
sub-queues paused
occurs for Queue 2
occurs for Queue 1
Queue State
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Inactive
shows the CCW format and an example of using pause to create sub-
Freescale Semiconductor, Inc.
Table 13-3 Queue 1 Priority Assertion
A trigger event for queue 1 or queue 2 causes the corresponding queue execution to
begin.
Queue 2 cannot begin execution until queue 1 reaches completion or the paused
state. The status register records the trigger event by reporting the queue 2 status as
trigger pending. Additional trigger events for queue 2, which occur before execution
can begin, are recorded as trigger overruns.
The current queue 2 conversion is aborted. The status register reports the queue 2
status as suspended. Any trigger events occurring for queue 2 while queue 2 is sus-
pended are recorded as trigger overruns. Once queue 1 reaches the completion or
the paused state, queue 2 begins executing again. The programming of the resume
bit in QACR2 determines which CCW is executed in queue 2.
Queue 1 begins execution and the queue 2 status is changed to trigger pending.
The pause feature can be used to divide queue 1 and/or queue 2 into multiple sub-
queues. A sub-queue is defined by setting the pause bit in the last CCW of the sub-
queue.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Result
Table 13-3
shows the condi-
MOTOROLA
13-15