MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 445

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QADC64MCR — QADC64 Module Configuration Register
13.12.1 QADC64 Module Configuration Register
RESET:
13.12.2 QADC64 Test Register
QADC64TEST — QADC64 Test Register
13.12.3 QADC64 Interrupt Register
QADC64INT — QADC64 Interrupt Register
MPC555
USER’S MANUAL
RESET:
STOP
Bit(s)
MSB
9:15
MSB
2:7
0
0
0
1
8
0
0
All QADC64 analog channel/port pins that are not used for analog input channels can
be used as digital port pins. Port values are read/written by accessing the port A and
B data registers (PORTQA and PORTQB). Port A pins are specified as inputs or out-
puts by programming the port data direction register (DDRQA). Port B is an input-only
port.
Used for factory test only.
FRZ
/
1
0
1
0
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Name
STOP
SUPV
FRZ
—
—
IRL1
2
0
2
0
Low-power stop mode enable. When the STOP bit is set, the clock signal to the QADC64 is dis-
abled, effectively turning off the analog circuitry.
0 = Enable QADC64 clock
1 = Disable QADC64 clock
assertion of the IMB3 FREEZE signal.
0 = QADC64 ignores the IMB3 FREEZE signal
1 = QADC64 finishes any current conversion, then freezes
Reserved
sor or unrestricted.
0 = Only the module configuration register, test register, and interrupt register are designated as
1 = All QADC64 registers and tables are designated as supervisor-only data space
Reserved
FREEZE assertion response. The FRZ bit determines whether or not the QADC64 responds to
Supervisor/unrestricted data space. The SUPV bit designates the assignable space as supervi-
3
0
3
0
supervisor-only data space. Access to all other locations is unrestricted
Table 13-7 QADC64MCR Bit Descriptions
Freescale Semiconductor, Inc.
RESERVED
4
0
For More Information On This Product,
4
0
5
0
5
0
Go to: www.freescale.com
Rev. 15 October 2000
6
0
6
0
IRL2
7
0
7
0
SUPV
8
1
Description
8
0
9
0
9
0
10
0
10
0
11
11
0
0x30 4802, 0x30 4C02
0
RESERVED
RESERVED
12
12
0
0
13
13
0
0
0x30 4C00
0x30 4800
0x30 4C04
0x30 4804
MOTOROLA
14
0
14
0
13-33
LSB
LSB
15
0
15
0