MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 470

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.5.6 QSMCM Test Register (QTEST)
14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
QDSCI_IL — QSM2 Dual SCI Interrupt Level Register
MPC555
USER’S MANUAL
RESET:
MSB
Bit(s)
Bit(s)
12:15
9:11
0
0
8:15
The QTEST register is used for factory testing of the MCU.
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the
QSMCM. The two SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI.
The QSPI uses a separate field, ILQSPI. The level value is used to determine which
interrupt is serviced first when two or more modules or external peripherals simulta-
neously request an interrupt. The user can select among 32 levels. This register can
be accessed only when the CPU is in supervisor mode.
2:7
0:2
3:7
0
1
8
Reserved
/
MPC556
1
0
ILDSCI
Name
STOP
SUPV
Name
FRZ1
IARB
—
—
—
—
2
0
3
0
Table 14-4 QSMCMMCR Bit Descriptions
Stop enable. Refer to
0 = Normal clock operation
1 = Internal clocks stopped
Freeze1 bit. Refer to
0 = Ignore the FREEZE signal
1 = Halt the QSMCM (on transfer boundary)
Reserved
Supervisor /Unrestricted. Refer to
0 = Assigned registers are unrestricted (user access allowed)
1 = Assigned registers are restricted (only supervisor access allowed)
Reserved
This field currently has no effect. It is implemented for future interrupt arbitration
schemes.
Reserved
Interrupt level of SCIs
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
Reserved
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-5 QDSCI_IL Bit Descriptions
For More Information On This Product,
4
0
ILDSCI
5
0
Go to: www.freescale.com
Rev. 15 October 2000
6
0
14.5.2 Freeze
14.5.1 Low-Power Stop
7
0
14.5.3 Access
8
Operation.
Description
Description
9
Operation.
10
Protection.
RESERVED
11
12
13
0x30 5004
MOTOROLA
14
LSB
14-8
15