MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 482

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.1.5 QSPI Status Register
SPSR — QSPI Status Register
MPC555
USER’S MANUAL
Bit(s)
MSB
8:15
0:4
0
5
6
7
The SPSR contains information concerning the current serial transmission. Only the
QSPI can set bits in this register. To clear status flags, the CPU reads SPSR with the
flags set and then writes the SPSR with zeros in the appropriate bits. Writes to CPTQP
have no effect.
*See bit descriptions in
1
/
LOOPQ
MPC556
Name
HMIE
HALT
—
—
2
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 = Feedback path disabled.
1 = Feedback path enabled.
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
from which it can later be restarted. Refer to
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
SPSR.
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
3
SPCR3*
Table
SeeTable 14-18
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
4
Table 14-17 SPCR3 Bit Descriptions
For More Information On This Product,
14-17.
5
Go to: www.freescale.com
Rev. 15 October 2000
for bit descriptions.
6
7
SPIF
8
0
Description
14.7.4.1 Enabling, Disabling, and Halting the
MODF
9
0
HAL-
TA
10
0
11
0
12
0
CPTQP
13
0
0x30 501E
MOTOROLA
14
0
14-20
LSB
15
SPI.
0