MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 483

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.2 QSPI RAM
MPC555
USER’S MANUAL
Bit(s)
11:15
0:7
10
8
9
The QSPI contains a 160-byte block of dual-ported static RAM that can be accessed
by both the QSPI and the CPU. Because of this dual access capability, up to two wait
states may be inserted into CPU access time if the QSPI is in operation.
The size and type of access of the QSPI RAM by the CPU affects the QSPI access
time. The QSPI allows byte, half-word, and word accesses. Only word accesses of the
RAM by the CPU are coherent because these accesses are an indivisible operation.
If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot access the
QSPI RAM until the CPU is finished. However, a word or misaligned word access is
not coherent because the CPU must break its access of the QSPI RAM into two parts,
which allows the QSPI to access the QSPI RAM between the two accesses by the
CPU.
The RAM is divided into three segments: receive data RAM, transmit data RAM, and
command data RAM. Receive data is information received from a serial device exter-
nal to the MCU. Transmit data is information stored for transmission to an external de-
vice. Command data defines transfer parameters.
organization.
/
CPTQP
SPCR3
HALTA
MODF
MPC556
Name
SPIF
See bit descriptions in
QSPI finished flag. SPIF is set after execution of the command at the address in ENDQP in
SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the
command defined by ENDQP, each time the QSPI cycles through the queue.
0 = QSPI is not finished
1 = QSPI is finished
Mode fault flag. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the
SS input pin is negated by an external driver. Refer to
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
Halt acknowledge flag. HALTA is set when the QSPI halts in response to setting the HALT bit in
SPCR3. HALTA is also set when the IMB3 FREEZE signal is asserted, provided the FRZ1 bit in
the QSMCMMCR is set. To prevent undefined operation, the user must not modify any QSPI
control registers or RAM while the QSPI is halted.
If HMIE in SPCR3 is set the QSPI sends interrupt requests to the CPU when HALTA is asserted.
0 = QSPI is not halted.
1 = QSPI is halted
Completed queue pointer. CPTQP points to the last command executed. It is updated when the
current command is complete. When the first command in a queue is executing, CPTQP contains
either the reset value 0x0 or a pointer to the last command completed in the previous queue.
If the QSPI is halted, CPTQP may be used to determine which commands have not been exe-
cuted. The CPTQP may also be used to determine which locations in the receive data segment
of the QSPI RAM contain valid received data.
in master mode (SS input taken low).
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Table 14-18 SPSR Bit Descriptions
Go to: www.freescale.com
Table
Rev. 15 October 2000
14-17.
Description
14.7.8 Mode Fault
Figure 14-5
for more information.
shows RAM
MOTOROLA
14-21