MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 496

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.5.1 Clock Phase and Polarity
14.7.5.2 Baud Rate Selection
MPC555
USER’S MANUAL
QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set,
the QSPI executes the command at the command RAM address pointed to by
NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer
and transmitted. Data that is simultaneously received is stored at the pointer address
in receive RAM.
When the proper number of bits have been transferred, the QSPI stores the working
queue pointer value in CPTQP, increments the working queue pointer, and loads the
next data for transfer from transmit RAM. The command pointed to by the incremented
working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven
to specified states during and between transfers. If the chip-select pattern changes
during or between transfers, the original pattern is driven until execution of the follow-
ing transfer begins. When CONT is cleared, the data in register PORTQS is driven be-
tween transfers. The data in PORTQS must match the inactive states of SCK and any
peripheral chip-selects used.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
In master mode, data transfer is synchronized with the internally-generated serial
clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity.
Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing
data from the MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from two to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive the SCK baud rate from the MCU IMB
clock.
The following expressions apply to the SCK baud rate:
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
SPBR
SCK Baud Rate
Rev. 15 October 2000
=
------------------------------------------------------------------------- -
2 SCK Baud Rate Desired
¥
=
or
------------------------- -
2
f SYS
f SYS
¥
SPBR
MOTOROLA
14-34