MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 503

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC555LFMZP40
Manufacturer:
MOTOLOLA
Quantity:
853
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Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC555LFMZP40
Manufacturer:
MOT
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Part Number:
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Manufacturer:
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14.7.8 Mode Fault
14.8 Serial Communication Interface
MPC555
USER’S MANUAL
Wraparound mode is properly exited in two ways: a) The CPU may disable wrap-
around mode by clearing WREN. The next time end of the queue is reached, the QSPI
sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method
halts the QSPI after the current transfer is completed, allowing the CPU to negate
SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method
is not recommended, as it causes the QSPI to abort a serial transfer in process.
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and
the slave select (PCS[0]/SS) input pin is pulled low by an external driver. This is pos-
sible only if the PCS[0]/SS pin is configured as input by QDDR. This low input to SS is
not a normal operating condition. It indicates that a multimaster system conflict may
exist, that another MCU is requesting to become the SPI network master, or simply
that the hardware is incorrectly affecting PCS[0]/SS. SPE in SPCR1 is cleared, dis-
abling the QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE
in SPCR3 is asserted, the QSPI generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing
SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be
re-enabled by asserting SPE.
The PCS[0]/SS pin may be configured as a general-purpose output instead of input to
the QSPI. This inhibits the mode fault checking function. In this case, MODF is not
used by the QSPI.
The dual, independent, serial communication interface (DSCI) communicates with ex-
ternal devices through an asynchronous serial bus. The two SCI modules are function-
ally equivalent, except that the SCI1 also provides 16-deep queue capabilities for the
transmit and receive operations. The SCIs are fully compatible with other Motorola SCI
systems. The DSCI has all of the capabilities of previous SCI systems as well as sev-
eral significant new features.
Figure 14-12
gram of the SCI receiver.
/
MPC556
is a block diagram of the SCI transmitter.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Figure 14-13
is a block dia-
MOTOROLA
14-41

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