MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 515

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
SCCxR1 determines whether TXD is an open drain (wired-OR) output or a normal
CMOS output. An external pull-up resistor on TXD is necessary for wired-OR opera-
tion. WOMS controls TXD function, regardless of whether the pin is used by the SCI
or as a general-purpose output pin.
Data to be transmitted is written to SCxDR, then transferred to the serial shifter. Before
writing to TDRx, the user should check the transmit data register empty (TDRE) flag
in SCxSR. When TDRE = 0, the TDRx contains data that has not been transferred to
the shifter. Writing to SCxDR again overwrites the data. If TDRE = 1, then TDRx is
empty, and new data may be written to TDRx, clearing TDRE.
As soon as the data in the transmit serial shifter has shifted out and if a new data frame
is in TDRx (TDRE = 0), then the new data is transferred from TDRx to the transmit se-
rial shifter and TDRE is set automatically. An interrupt may optionally be generated at
this point.
The transmission complete (TC) flag in SCxSR shows transmitter shifter state. When
TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is
not automatically cleared. The processor must clear it by first reading SCxSR while TC
is set, then writing new data to SCxDR, or writing to SCTQ[0:15] for transmit queue
operation.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame
is transmitted as a preamble to the following data frame. If TC = 0, the current opera-
tion continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The SBK bit in SCCxR1 is used to insert break frames in a transmission. A non-zero
integer number of break frames are transmitted while SBK is set. Break transmission
begins when SBK is set, and ends with the transmission in progress at the time either
SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmis-
sion finishes normally before the break begins. To ensure the minimum break time,
toggle SBK quickly to one and back to zero. The TC bit is set at the end of break trans-
mission. After break transmission, at least one bit-time of logic level one (mark idle) is
transmitted to ensure that a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE
and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data, and break
frames are transmitted. The TC flag is set, and control of the TXD pin reverts to
PQSPAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid
losing data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output, then write a one to either
QDTX1 or QDTX2 of the PORTQS register. See 14.6.1. When the transmitter releases
control of the TXD pin, it reverts to driving a logic one output.
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
14-53