MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 537

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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15.1 MIOS1 Features
MPC555 / MPC556
USER’S MANUAL
The modular I/O system (MIOS) consists of a library of flexible I/O and timer functions
including I/O port, counters, input capture, output compare, pulse and period measure-
ment, and PWM. Because the MIOS is composed of submodules, it is easily config-
urable for different kinds of applications. MIOS1 is the implementation of the MIOS
architecture used in the MPC555 / MPC556.
The MIOS1 is composed of the following submodules:
The basic features of the MIOS1 are as follows:
• One MIOS bus interface submodule (MBISM)
• One MIOS counter prescaler submodule (MCPSM)
• Two MIOS modulus counter submodules (MMCSM)
• 10 MIOS double action submodules (MDASM)
• Eight MIOS pulse width modulation submodules (MPWMSM)
• One MIOS 16-bit parallel port I/O submodule (MPIOSM)
• Two MIOS interrupt request submodules (MIRSM)
• Modular architecture at the silicon implementation level
• Disable capability in each submodule to allow power saving when its function is
• Two 16-bit buses to allow action submodules to use counter data
• When not used for timing functions, every channel pin can be used as a port pin:
• Submodules pin status bits:
• MIOS counter prescaler submodule (MCPSM):
• Two MIOS modulus counter submodules (MMCSM), each with these features:
not needed
I/O, output only or input only, depending on the channel function
— Centralized counter clock generator
— Programmable 4-bit modulus down-counter
— Wide range of possible division ratios: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
— Count inhibit under software control
— Programmable 16-bit modulus up-counter with built-in programmable 8-bit
— Maximum increment frequency of the counter:
— Flag setting and possible interrupt generation on overflow of the up-counter
— Time counter on internal clock with interrupt capability after a pre-determined
15 and 16
prescaler clocked by MCPSM output
• clocked by the internal Counter Clock: F
• clocked by the external pin: F
time
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
SECTION 15
SYS
/4
SYS
/2
MOTOROLA
15-1

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