MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 569

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers
MPC555
USER’S MANUAL
Within the MIOS1, each MIRSM includes:
One bit position in each of the above registers is associated with one submodule. Note
that if a submodule in a group of 16 cannot generate interrupts, then its corresponding
flag bit in the status register is inactive and reads as zero.
When an event occurs in a submodule that activates a flag line, the corresponding flag
bit in the status register is set. The status register is read/write, but a flag bit can be
reset only if it has previously been read as a one. Writing a one to a flag bit has no
effect. When the software intends to clear only one flag bit within a status register, the
software must write an 16-bit value of all ones except for a zero in the bit position to
be cleared.
The enable register is initialized by the software to indicate whether each interrupt re-
quest is enabled for the level defined in the ICS.
Each bit in the IRQ pending register is the result of a logical “AND” between the corre-
sponding bits in the status and in the enable registers. If a flag bit is set and the level
enable bit is also set, then the IRQ pending bit is set and the information is transferred
to the interrupt control section that is in charge of sending the corresponding level to
the CPU. The IRQ pending register is read only.
The submodule number of an interrupting source defines the corresponding MIRSM
number and the bit position in the status registers. To find the MIRSM number and bit
position of an interrupting source, divide the interrupting submodule number by 16.
The integer result of the division gives the MIRSM number. The remainder of the divi-
sion gives the bit position.
Refer to
15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers
about the registers in the MIRSM.
Table 15-28
• One 16-bit status register (for the flags)
• One 16-bit enable register
• One 16-bit IRQ pending register
/
MPC556
15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers
When the enable bit is not set for a particular submodule, the corre-
sponding status register bit is still set when the corresponding flag is
set. This allows the traditional software approach of polling the flag
bits to see which ones are set. The status register makes flag polling
easy, since up to sixteen flag bits are contained in one register.
shows the registers associated with the MIRSM0 submodule.
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
MOTOROLA
for details
and to
15-33