MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 570

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.14.2.1 MIRSM0 Interrupt Status Register (MIOS1SR0)
MIOS1SR0 — RQSM0 Interrupt Status Register
MPC555
USER’S MANUAL
FLG15 FLG14 FLG13 FLG12 FLG11
MSB
U
0
RESET:
This register contains flag bits that are set when the associated submodule generates
an interrupt. Each bit corresponds to a submodule.
When an event occurs in a submodule that activates a flag line, the corresponding flag
bit in the status register is set. The status register is read/write, but a flag bit can be
reset only if it has previously been read as a one. Writing a one to a flag bit has no
effect. When the software intends to clear only one flag bit within a status register, the
software must write an 16-bit value of all ones except for a zero in the bit position to
be cleared.
U
1
/
MPC556
0x30 6C00
0x30 6C02
0x30 6C04
0x30 6C06
U
2
Address
Bit(s)
10:11
5:8
12
13
14
15
0
1
2
3
4
9
U
3
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
MIRSM0 Interrupt Status Register (MIOS1SR0)
See
Reserved
MIRSM0 Interrupt Enable Register (MIOS1ER0)
See
MIRSM0 Request Pending Register (MIOS1RPR0)
See
Table 15-29 MIOS1SR0 Bit Descriptions
Freescale Semiconductor, Inc.
U
4
FLG15
FLG14
FLG13
FLG12
FLG11
For More Information On This Product,
Name
FLG6
FLG3
FLG2
FLG1
FLG0
Table 15-28 MIRSM0 Address Map
Table 15-29
Table 15-30
Table 15-31
—
—
5
0
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MDASM15 flag bit
MDASM14 flag bit
MDASM13 flag bit
MDASM12 flag bit
MDASM11 flag bit
Reserved
MMCSM6 flag bit
Reserved
MPWMSM3 flag bit
MPWMSM2 flag bit
MPWMSM1 flag bit
MPWMSM0 flag bit
RESERVED
Rev. 15 October 2000
6
0
for bit descriptions.
for bit descriptions.
for bit descriptions.
7
0
Register
8
0
Description
FLG6
U
9
RESERVED
10
U
11
U
FLG3
12
U
FLG2
13
U
0x30 6C00
MOTOROLA
FLG1
14
U
15-34
FLG0
LSB
15
U