MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 616

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

IMASK — Interrupt Mask Register
16.7.13 Interrupt Mask Register
MPC555
USER’S MANUAL
MSB
Bit(s)
Bit(s)
0
0
8:15
0:7,
RESET:
14
15
1
0
/
MPC556
WAKEINT
IMASKH,
ERRINT
IMASKL
Name
Name
2
0
BITERR[1:0]
Table 16-21 ESTAT Bit Descriptions (Continued)
3
0
00
01
10
11
IMASKH
Table 16-23 Fault Confinement State Encoding
Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a
transmit or receive error.
0 = No error interrupt request
1 = If an event which causes one of the error bits in the error and status register to be set
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
TouCAN module is in low-power stop mode.
0 = No wake interrupt requested
1 = When the TouCAN is in low-power stop mode and a recessive to dominant transition is
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16-
bit read or write, and IMASKH and IMASKL can be accessed with byte reads or writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buff-
ers will generate interrupts after successful transmission/reception. Setting a bit in IMASK
enables interrupt requests for the corresponding message buffer.
NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage
buffer 15.
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an in-
terrupt request is generated.
Freescale Semiconductor, Inc.
4
0
Table 16-22 Transmit Bit Error Status
Table 16-24 IMASK Bit Descriptions
For More Information On This Product,
No transmit bit error
At least one bit sent as dominant was received as recessive
At least one bit sent as recessive was received as dominant
Not used
FCS[1:0]
CAN 2.0B CONTROLLER MODULE
5
0
1X
00
01
Go to: www.freescale.com
Rev. 15 October 2000
6
0
7
0
Bit Error Status
8
0
Error passive
Error active
Bus State
Description
Description
Bus off
9
0
10
0
11
0x30 70A2, 0x30 74A2
0
IMASKL
12
0
13
0
MOTOROLA
14
0
16-34
LSB
15
0