MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 617

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

IFLAG — Interrupt Flag Register
RXECTR — Receive Error Counter
TXECTR — Transmit Error Counter
16.7.14 Interrupt Flag Register
16.7.15 Error Counters
MPC555
USER’S MANUAL
MSB
MSB
Bit(s)
Bit(s)
0
0
0
0
8:15
8:15
0:7,
0:7,
RESET:
RESET:
1
0
1
0
/
MPC556
RXECTR,
TXECTR
IFLAGH,
IFLAGL
Name
Name
2
0
2
0
3
0
3
0
Table 16-26 RXECTR, TXECTR Bit Descriptions
RXECTR
IFLAGH
IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a 16-bit
read or write, and IFLAGH and IFLAGL can be accessed with byte reads or writes.
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets
the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request
will be generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a
new flag setting event occur between the time that the CPU reads the flag as a one and
writes the flag as a zero, the flag is not cleared. This register can be written to zeros only.
NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage
buffer 15.
Both counters are read only, except when the TouCAN is in test or debug mode.
Freescale Semiconductor, Inc.
4
0
4
0
Table 16-25 IFLAG Bit Descriptions
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
5
0
5
0
Go to: www.freescale.com
Rev. 15 October 2000
6
0
6
0
7
0
7
0
8
0
8
0
Description
Description
9
0
9
0
10
10
0
0
11
11
0x30 70A6, 0x30 74A6
TXECTR
0
0
IFLAGL
12
12
0
0
13
13
0
0
0x30 70A4
0x30 74A4
MOTOROLA
14
14
0
0
16-35
LSB
LSB
15
15
0
0