MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 620

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.2 TPU3 Components
17.2.1 Time Bases
17.2.2 Timer Channels
17.2.3 Scheduler
17.2.4 Microengine
MPC555
USER’S MANUAL
The microcode ROM TPU3 functions that are available in the MPC555 / MPC556 are
described in
The TPU3 consists of two 16-bit time bases, 16 independent timer channels, a task
scheduler, a microengine, and a host interface. In addition, a dual-ported parameter
RAM is used to pass parameters between the module and the CPU.
Two 16-bit counters provide reference time bases for all output compare and input
capture events. Prescalers for both time bases are controlled by the CPU via bit fields
in the TPU3 module configuration register (TPUMCR) and TPU module configuration
register two (TPUMCR2). Timer count registers TCR1 and TCR2 provide access to the
current counter values. TCR1 and TCR2 can be read by TPU microcode but are not
directly available to the CPU. The TCR1 clock is always derived from the IMB clock.
The TCR2 clock can be derived from the IMB clock or from an external input via
theT2CLK clock pin. The duration between active edges on the T2CLK clock pin must
be at least nine IMB clocks.
The TPU3 has 16 independent channels, each connected to an MCU pin. The chan-
nels have identical hardware and are functionally equivalent in operation. Each chan-
nel consists of an event register and pin control logic. The event register contains a
16-bit capture register, a 16-bit compare/match register, and a 16-bit greater-than-or-
equal-to comparator. The direction of each pin, either output or input, is determined by
the TPU microengine. Each channel can either use the same time base for match and
capture, or can use one time base for match and the other for capture.
When a service request is received, the scheduler determines which TPU3 channel is
serviced by the microengine. A channel can request service for one of four reasons:
for host service, for a link to another channel, for a match event, or for a capture event.
The host system assigns each active channel one of three priorities: high, middle, or
low. When multiple service requests are received simultaneously, a priority-scheduling
mechanism grants service based on channel number and assigned priority.
The microengine is composed of a control store and an execution unit. Control-store
ROM holds the microcode for each factory-masked time function. When assigned to a
channel by the scheduler, the execution unit executes microcode for a function as-
signed to that channel by the CPU. Microcode can also be executed from the dual-port
RAM (DPTRAM) module instead of the control store. The DPTRAM allows emulation
and development of custom TPU microcode without the generation of a microcode
ROM mask. Refer to
/
MPC556
APPENDIX D TPU ROM
Freescale Semiconductor, Inc.
17.3.6 Emulation Support
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
FUNCTIONS.
for more information.
MOTOROLA
17-2