MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 629

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
12:15
1:2
3:4
10
11
0
5
6
7
8
9
/
TCR1P
TCR2P
T2CSL
MPC556
Name
STOP
T2CG
SUPV
PSCK
TPU3
EMU
STF
—
Low-power stop mode enable. If the STOP bit in TPUMCR is set, the TPU3 shuts down its inter-
nal clocks, shutting down the internal microengine. TCR1 and TCR2 cease to increment and re-
tain the last value before the stop condition was entered. The TPU3 asserts the stop flag (STF)
in TPUMCR to indicate that it has stopped.
0 = Enable TPU3 clocks
1 = Disable TPU3 clocks
Timer count register 1 prescaler control. TCR1 is clocked from the output of a prescaler. The
prescaler divides its input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
Refer to
Timer count register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The
prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
Refer to
Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM ex-
clusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for use
by the TPU3. After reset, this bit can be written only once.
0 = TPU3 and DPTRAM operate normally
1 = TPU3 and DPTRAM operate in emulation mode
TCR2 clock/gate control
0 = TCR2 pin used as clock source for TCR2
1 = TCR2 pin used as gate of DIV8 clock for TCR2
Refer to
Stop flag.
0 = TPU3 is operating normally
1 = TPU3 is stopped (STOP bit has been set)
Supervisor data space
0 = Assignable registers are accessible from user or supervisor privilege level
1 = Assignable registers are accessible from supervisor privilege level only
Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected
(EPSCKE = 1).
0 = f
1 = f
TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on
the TPU3, the microcode size should not be greater than two Kbytes and the TPU3 enable bit
should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one,
meaning that the TPU3 will operate in TPU3 mode.
0 = TPU mode; zero is the TPU reset value
1 = TPU3 mode; one is the TPU3 reset value
NOTE: The programmer should not change this value unless necessary when developing cus-
tom TPU microcode.
TCR2 counter clock edge. This bit and the T2CG control bit determine the clock source for TCR2.
Refer to
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TPU3 implementa-
tions that use hardware interrupt arbitration.
SYS
SYS
Freescale Semiconductor, Inc.
17.3.8 Prescaler Control for TCR1
17.3.9 Prescaler Control for TCR2
17.3.9 Prescaler Control for TCR2
÷ 32 is input to TCR1 prescaler, if standard prescaler is selected
÷ 4 is input to TCR1 prescaler, if standard prescaler is selected
17.3.9 Prescaler Control for TCR2
Table 17-6 TPUMCR Bit Descriptions
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
Description
for more information.
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MOTOROLA
17-11