MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 692

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.10.3 Emulation Operation
19.11 Disabling the CMF Module
MPC555
USER’S MANUAL
The CMF EEPROM supports externally mapped access for emulation operation.
When the SIU indicates an externally mapped access to the CMF EEPROM, the CMF
does not respond to the address, even though it may be a valid CMF access. Refer to
10.6 Dual Mapping of the Internal Flash EEPROM Array
The CMF EEPROM can be disabled when the internal memories are disabled. Dis-
abling the internal memories is controlled by the FLEN bit (bit 20) in the USIU internal
memory map register. The default reset enable/disable state of the internal memories
is user defined with the reset configuration word bit 20.
EHV is reset to 0 when the CMF is disabled and can not be set until the CMF is en-
abled, see section
the power used by the CMF is reduced.
/
MPC556
The reset configuration word from an erased CMF must be generat-
ed external to the CMF, i.e., from the default reset configuration word
off the external reset configuration word. See
tion.
Although the program and erase operations can be suspended (EHV
= 0) by disabling the internal memory, it is not recommended that pro-
gram or erase be suspended in this manner.
19.7.8 Controlling the Program/Erase Voltage
Freescale Semiconductor, Inc.
For More Information On This Product,
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
CAUTION
NOTE
7.5 Reset Configura-
for details.
When disabled,
MOTOROLA
19-40