MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 695

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

20.3.2 SRAM Test Register (SRAMTST)
SRAMTST — SRAM Test Register
MPC555
USER’S MANUAL
SRAMMCR — SRAM Module Configuration Register
20, 23, 26,
21, 24, 27,
22, 25, 28,
MSB
LCK
16
Bit(s)
0
0
0
RESET:
RESET:
3:19
The SRAM test register is used for factory testing only.
29
30
31
0
1
2
RESERVED
DIS
17
/
1
0
0
MPC556
(x = 0, 1, 2, 3)
(x = 0, 1, 2, 3)
(x = 0, 1, 2, 3)
2CY
18
Name
2
0
0
LCK
2CY
DIS
Rx
Dx
Sx
—
19
3
0
0
Lock bit. This bit can be set only once and cleared only by reset.
0 = Writes to the SRAMMCR are accepted
1 = Writes to the SRAMMCR are ignored
Module disable
0 = SRAM module is enabled
1 = SRAM module is disabled. Module can be subsequently re-enabled by software set-
Two-cycle mode
0 = SRAM module is in single-cycle mode (normal operation)
1 = SRAM module is in two-cycle mode. In this mode, the first cycle is used for decoding
Reserved
Read only. R0 controls the highest 4-Kbyte block (lowest address) of the SRAM array;
R3 controls the lowest block (highest address).
0 = 4-Kbyte block is readable and writable
1 = 4-Kbyte block is read only. Attempts to write to this space result in internal TEA as-
Data only. D0 controls the highest 4-Kbyte block (lowest address) of the SRAM array; D3
controls the lowest block (highest address).
0 = 4-Kbyte block can contain data or instructions
1 = 4-Kbyte block contains data only. Attempts to load instructions from this space result
Supervisor only. S0 controls the highest 4-Kbyte block (lowest address) of the SRAM ar-
ray; S3 controls the lowest block (highest address).
0 = 4-Kbyte block is placed in unrestricted space
1 = 4-Kbyte block is placed in supervisor space. Attempts to access this space from the
Table 20-1 SRAMMCR Bit Descriptions
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
R0
20
4
0
0
For More Information On This Product,
ting this bit or by reset. Attempts to read SRAM array when it is disabled result in
internal TEA assertion.
the address, and the second cycle is used for accepting or providing data. This
mode provides some power savings while keeping the memory active.
sertion.
in internal TEA assertion.
user privilege level result in internal TEA assertion.
D0
21
5
0
0
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Rev. 15 October 2000
22
S0
6
0
0
R1
23
7
0
0
D1
24
8
0
0
RESERVED
Description
25
S1
9
0
0
R2
10
26
0
0
D2
11
27
0
0
0x38 0004, 0x38 000C
12
28
S2
0
0
R3
13
29
0
0
0x38 0000
0x38 0008
MOTOROLA
D3
14
30
0
0
LSB
15
31
S3
20-3
0
0