MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 708

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
• Two L-data comparators (each supports equal, not equal, greater than, less than)
• No internal breakpoint/watchpoint matching support for unaligned words and half-
• The L-data comparators can be programmed to treat fix point numbers as signed
• Combine comparator pairs to detect in and out of range conditions (including ei-
• A programmable AND-OR logic structure between the four instruction compara-
• A programmable AND-OR logic structure between the four instruction watch-
• Five watchpoint pins, three for the instruction and two for the load/store
• Two dedicated 16-bit down counters. Each can be programmed to count either
• On the fly trap enable programming of the different internal breakpoints using the
• Watchpoints do not change the timing of the machine
• Internal breakpoints and watchpoints are detected on the instruction during in-
• Internal breakpoints and watchpoints are detected on the load/store during load/
• Both instruction and load/store breakpoints and watchpoints are handled and re-
• Instructions with instruction breakpoints are not executed. The machine branches
• Instructions with load/store breakpoints are executed. The machine branches to
• Load/store multiple and string instructions with load/store breakpoints first finish
• Load/store data compare is done on the load/store, AFTER swap in store access-
• Internal breakpoints may operate either in masked mode or in non-masked mode.
/
than) including least significant bits masking according to the size of the bus cycle
for the byte and half-word working modes. Refer to
Working Modes
including byte, half-word and word operating modes and four byte mask bits for
each comparator. Can be used for fix point data. Match is detected only on the
valid part of the data bus (according to the cycle’s size and the two address least
significant bits).
words
values or as unsigned values
ther signed or unsigned values on the L-data)
tors results with five outputs, four instruction watchpoints and one instruction
breakpoint
points and the four load/store comparators results with three outputs, two load/
store watchpoints and one load/store breakpoint
an instruction watchpoint or an load/store watchpoint. Only architecturally execut-
ed events are counted, (count up is performed in case of recovery).
serial interface of the development port (refer to
ware control is also available.
struction fetch
store bus cycles
ported on retirement. Breakpoints and watchpoints on recovered instructions (as
a result of exceptions, interrupts or miss prediction) are not reported and do not
change the timing of the machine.
to the breakpoint exception routine BEFORE it executes the instruction.
the breakpoint exception routine AFTER it executes the instruction. The address
of the access is placed in the BAR (breakpoint address register).
execution (all of it) and then the machine branches to the breakpoint exception
routine.
es and BEFORE swap in load accesses (as the data appears on the bus).
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21.5 Development
21.3.1.2 Byte and Half-Word
Port). Soft-
MOTOROLA
21-12