MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 726

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.4.1.5 Running in Debug Mode
21.4.1.6 Exiting Debug Mode
MPC555
USER’S MANUAL
have some significant value, these two registers must be saved before any other op-
eration is performed. Failing to save these registers may result in loss of their value in
case of another load/store type exception inside the development software.
Since exceptions are treated differently when in debug mode (refer to
ning in Debug
ister (SRR0) and machine status save/restore one register (SRR1).
When running in debug mode all fetch cycles access the development port regardless
of the actual address of the cycle. All load/store cycles access the real memory system
according to the cycle’s address. The data register of the development port is mapped
as a special control register therefore it is accessed using mtspr and mfspr instruc-
tions via special load/store cycles (refer to
(DPDR)).
Exceptions are treated differently when running in debug mode. When already in de-
bug mode, upon recognition of an exception, the exception cause register (ECR) is up-
dated according to the event that caused the exception, a special error indication
(ECR_OR) is asserted for one clock cycle to report to the development port that an
exception occurred and execution continues in debug mode without any change in
SRR0 and SRR1. ECR_OR is asserted before the next fetch occurs to allow the de-
velopment system to detect the excepting instruction.
Not all exceptions are recognized when in debug mode. Breakpoints and watchpoints
are not generated by the hardware when in debug mode (regardless of the value of
MSRRI). Upon entering debug mode MSREE is cleared by the hardware thus forcing
the hardware to ignore external and decrementer interrupts.
Setting the MSREE bit while in debug mode, (by the debug software), is strictly forbid-
den. The reason for this restriction is that the external interrupt event is a level signal,
and since the CPU only reports exceptions while in debug mode but do not treat them,
the CPU does not clear the MSREE bit and, therefore, this event, if enabled, is recog-
nized again every clock cycle.
When the ECR_OR signal is asserted the development station should investigate the
exception cause register (ECR) in order to find out the event that caused the excep-
tion.
Since the values in SRR0 and SRR1 do not change if an exception is recognized while
already in debug mode, they only change once when entering debug mode, saving
them when entering debug mode is not necessary.
The rfi instruction is used to exit from debug mode in order to return to the normal pro-
cessor operation and to negate the freeze indication. The development system may
monitor the freeze status to make sure the MPC555 / MPC556 is out of debug mode.
It is the responsibility of the software to read the exception cause register (ECR) before
/
MPC556
Mode), there is no need to save machine status save/restore zero reg-
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21.7.13 Development Port Data Register
21.4.1.5 Run-
MOTOROLA
21-30