MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 751

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.7.12 Debug Enable Register (DER)
MPC555
USER’S MANUAL
DER — Debug Enable Register
Bit(s)
SERV
Bit(s)
RE-
ED
16
0:1
4:5
28
29
30
31
0
0
0
0
1
2
3
RESET:
RESET:
This register enables the user to selectively mask the events that may cause the pro-
cessor to enter into debug mode.
RSTE
SEEE
17
/
1
0
0
CHSTPE
Name
EBRK
MPC556
LBRK
IBRK
MCEE
DPI
Name
RSTE
—
—
CHST
SERV
RE-
PE
ED
18
2
1
0
L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store break-
point. Results in debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction break-
point. Results in debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip
IMB or L-bus module, or by an external device or development system through the development
port). This bit is set as a result of the assertion of an external breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
Development port interrupt bit. Set by the development port as a result of a debug station non-
maskable request or when debug mode is entered immediately out of reset.
MCEE
BERE
ITL-
Reserved
Reset enable
0 = Debug entry is disabled (reset value)
1 = Debug entry is enabled
Checkstop enable bit
0 = Debug mode entry disabled
1 = Debug mode entry enabled (reset value)
Machine check exception enable bit
0 = Debug mode entry disabled (reset value)
1 = Debug mode entry enabled
Reserved
19
3
0
0
Table 21-27 ECR Bit Descriptions (Continued)
SERV
Freescale Semiconductor, Inc.
RESERVED
RE-
ED
20
4
0
0
For More Information On This Product,
Table 21-28 DER Bit Descriptions
BERE
DTL-
21
5
0
0
DEVELOPMENT SUPPORT
Go to: www.freescale.com
EXTIE ALEE PREE
Rev. 15 October 2000
22
6
0
0
23
7
0
0
RESERVED
24
8
0
0
Description
Description
FPU-
VEE
25
9
0
0
CEE
DE-
10
26
0
0
RESERVED
11
27
0
0
LBRK
12
28
E
0
1
IBRKE
SEE
SY-
13
29
0
1
MOTOROLA
EBRK
SPR 149
TRE
14
30
E
1
1
FPAS
DPIE
21-55
15
31
E
0
1