MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 755

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

22.1 JTAG Interface Block Diagram
MPC555 / MPC556
USER’S MANUAL
The MPC555 / MPC556 includes dedicated user-accessible test logic that is fully com-
patible with the IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Ar-
chitecture. Problems associated with testing high-density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Commit-
tee of IEEE and the Joint Test Action Group (JTAG). The MPC555 / MPC556 supports
circuit-board test strategies based on this standard.
This section is intended to be used with the supporting IEEE 1149.1-1990 standard.
The scope of this description includes those items required by the standard to be de-
fined and, in certain cases, provides additional information specific to the implementa-
tion. For internal details and applications of the standard, refer to the IEEE 1149.1-
1990 document.
An overview of the JTAG pins on the MPC555 / MPC556 is shown in
Boundary scan cells (BSC) are placed at the digital boundary of the chip (normally the
package pins). The boundary scan cells are chained together to form a boundary scan
register (BSR). The data is serially shifted in through the serial port (TDI) and serially
shifted out through the output port (TDO).
A block diagram of the MPC555 / MPC556 implementation of the IEEE 1149.1-1990
test logic is shown in
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
Freescale Semiconductor, Inc.
JCOMP
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
Figure
For More Information On This Product,
TMS
TDO
TCK
TDI
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Figure 22-1 JTAG Pins
22-2.
Go to: www.freescale.com
Rev. 15 October 2000
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SECTION 22
MPC555 / MPC556
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TRST
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Figure
MOTOROLA
22-1.
22-1