MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 759

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

22.5.1 EXTEST
22.5.2 SAMPLE/PRELOAD
22.5.3 BYPASS
MPC555
USER’S MANUAL
The parallel output of the instruction register is reset to all ones in the test-logic-reset
controller state. Note that this preset state is equivalent to the BYPASS instruction.
During the capture-IR controller state, the parallel inputs to the instruction shift register
are loaded with the CLAMP command code.
The external test (EXTEST) instruction selects the 346-bit boundary scan register. EX-
TEST also asserts internal reset for the MPC555 / MPC556 system logic to force a pre-
dictable beginning internal state while performing external boundary scan operations.
By using the TAP, the register is capable of scanning user-defined values into the out-
put buffers, capturing values presented to input pins and controlling the output drive of
three-state output or bi-directional pins. For more details on the function and use of
EXTEST, refer to the scan chain document.
The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells
prior to selection of EXTEST. This initialization ensures that known data will appear on
the outputs when entering the EXTEST instruction. The SAMPLE/PRELOAD instruc-
tion also provides a means to obtain a snapshot of system data and control signals.
The BYPASS instruction selects the single-bit bypass register as shown in
4. This creates a shift register path from TDI to the bypass register and, finally, to TDO,
circumventing the 463-bit boundary scan register. This instruction is used to enhance
test efficiency when a component other than the MPC555 / MPC556 becomes the de-
vice under test.
/
MPC556
Since there is no internal synchronization between the scan chain
clock (TCK) and the system clock (CLKOUT), the user must provide
some form of external synchronization to achieve meaningful results.
Freescale Semiconductor, Inc.
B3
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
0
0
0
0
0
For More Information On This Product,
Table 22-2 Instruction Decoding
B2
X
0
0
1
1
Go to: www.freescale.com
Code
Rev. 15 October 2000
B1
0
0
1
0
0
B0
NOTE
X
0
1
0
1
EXTEST
SAMPLE/PRELOAD
BYPASS
HI-Z
CLAMP and BYPASS
Instruction
MOTOROLA
Figure 22-
22-5