MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 843

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

D.11 Fast Quadrature Decode TPU Function (FQD)
MPC555 / MPC556
USER’S MANUAL
FQD is a position feedback function for motor control. It decodes the two signals from
a slotted encoder to provide the CPU with a 16-bit free-running position counter. FQD
incorporates a “speed switch” which disables one of the channels at high speed, al-
lowing faster signals to be decoded. A time stamp is provided on every counter update
to allow position interpolation and better velocity determination at low speed or when
low resolution encoders are used. The third index channel provided by some encoders
is handled by the ITC function. See Motorola TPU Progamming Note
Decode TPU Function (FQD), (TPUPN02/D).
Figure D-19
primary and secondary channels, respectively.
and
Figure D-20
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TPU ROM FUNCTIONS
show the host interface areas for the FQD function for
Rev. 15 October 2000
Fast Quadrature
MOTOROLA
D-29