PIC16C774-I/L Microchip Technology, PIC16C774-I/L Datasheet - Page 63
![IC MCU OTP 4KX14 A/D PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16C774-I/L
Manufacturer Part Number
PIC16C774-I/L
Description
IC MCU OTP 4KX14 A/D PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C773SO.pdf
(201 pages)
3.PIC16C774P.pdf
(13 pages)
4.PIC16C774P.pdf
(16 pages)
Specifications of PIC16C774-I/L
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164309 - MODULE SKT FOR PM3 44PLCCISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16C774-04I/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C774-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C773SO PDF datasheet #2
- PIC16C774P PDF datasheet #3
- PIC16C774P PDF datasheet #4
- Current page: 63 of 201
- Download datasheet (3Mb)
8.2
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit address-
ing.
Refer to Application Note AN578, "Use of the SSP
Module in the I
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
FIGURE 8-10: I
1999 Microchip Technology Inc.
SDA
SCL
MSSP I
2
Read
clock
C Multi-Master Environment."
shift
2
DIAGRAM
2
C Operation
C SLAVE MODE BLOCK
MSb
Stop bit detect
SSPBUF reg
Match detect
SSPADD reg
2
SSPSR reg
Start and
C mode fully implements all
LSb
Write
(SSPSTAT reg)
data bus
Internal
Set, Reset
S, P bits
Addr Match
Advance Information
FIGURE 8-11: I
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
Before selecting any I
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
sible
SDA
SCL
Baud Rate Generator
2
2
2
SSPADD<6:0>
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode, clock = OSC/4 (SSPADD +1)
7
Read
clock
shift
DIAGRAM
2
C MASTER MODE BLOCK
MSb
2
Start and Stop bit
2
detect / generate
C modes to be selected:
2
C mode, the SCL and SDA pins
Match detect
SSPADD reg
C mode is enabled. The SSP
SSPBUF reg
SSPSR reg
PIC16C77X
2
2
C mode, by setting the
C mode.
LSb
DS30275A-page 63
Write
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
data bus
2
Internal
C operation.
Addr Match
and
2
C opera-
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