AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1060

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.7.5.4
43.7.5.5
43.7.5.6
43.7.5.7
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AT91SAM9M10
Wake-up Triggered by the AC97 Codec
AC97 Codec Reset
Cold AC97 Reset
Warm AC97 Reset
The AC97 Controller can also wake up the AC97 Codec by asserting AC97FS signal, however
this action should not be performed for a minimum period of four audio frames following the
frame in which the powerdown was issued.
This feature is implemented in AC97 modem codecs that need to report events such as Caller-
ID and wake-up on ring.
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the
controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously
(regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR
register, an interrupt is triggered that wakes up the AC97 Controller which should then immedi-
ately issue a cold or a warm reset.
If the processor needs to be awakened by an external event, the AC97RX signal must be exter-
nally connected to the WAKEUP entry of the system controller.
Figure 43-7. AC97 Power-Down/Up Sequence
There are three ways to reset an AC97 Codec.
A cold reset is generated by asserting the RESET signal low for the minimum specified time
(depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS
is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers
on AC-link can resume.
The RESET signal will be controlled via a PIO line. This is how an application should perform a
cold reset:
AC97CK, the clock provided by AC97 Codec, is detected by the controller.
A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is sig-
naled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the
• Clear and set ENA flag in the AC97C_MR register to reset the AC97 Controller
• Clear PIO line output controlling the AC97 RESET signal
• Wait for the minimum specified time
• Set PIO line output controlling the AC97 RESET signal
AC97CK
AC97RX
AC97FS
AC97TX
TAG
TAG
Power Down Frame
Write to
Write to
0x26
0x26
Data
Data
PR4
PR4
Sleep State
Wake Event
Warm Reset
TAG
TAG
New Audio Frame
6355B–ATARM–21-Jun-10
Slot1
Slot1
Slot2
Slot2