AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 940
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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40.8
940
Conversion Results
AT91SAM9M10
When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and
stored in the
“TSADCC Last Converted Data
The channel EOC bit and the bit DRDY in the
PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and
DRDY can trigger an interrupt.
Reading one of the
sponding EOC bit.
Reading
sponding to the last converted channel.
Figure 40-5. EOCx and DRDY Flag Behavior
If the
converted, the corresponding Overrun Error (OVRE) flag is set in the
Register”.
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in the
The OVRE and GOVRE flags are automatically cleared when the
read.
“TSADCC Channel Data Register x (x = 0..7)”
(ADC_CHSR)
“TSADCC Last Converted Data Register”
(ADC_SR)
(ADC_SR)
EOCx
DRDY
“TSADCC Status
“TSADCC Channel Data Register x (x = 0..7)”
CHx
Write the ADC_CR
with START = 1
“TSADCC Channel Data Register x (x = 0..7)”
SHTIM
Conversion
Register”.
Time
Register”.
Read the ADC_CDRx
“TSADCC Status Register”
clears the DRDY bit and the EOC bit corre-
is not read before further incoming data is
Write the ADC_CR
with START = 1
of the current channel and in the
SHTIM
“TSADCC Status
Conversion
registers clears the corre-
Time
Read the ADC_LCDR
6355B–ATARM–21-Jun-10
are both set. If the
“TSADCC Status
Register”is
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