Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 40
Z8F0431SJ020SG
Manufacturer Part Number
Z8F0431SJ020SG
Description
IC ENCORE XP MCU FLASH 4K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F0431SJ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4627-5
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
Z8F0431SJ020SG
Manufacturer:
Zilog
Quantity:
784
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Table 11. Reset Status Register (RSTSTAT)
Debug Pin Driven Low
Reset Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
Stop Mode Recovery Using the External RESET Pin
Reset Status Register
POR
R
7
When the Z8 Encore!
is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin,
the low pulse must be greater than the minimum width specified about 12 ns, or it is
ignored. The EXT bit in the reset status (RSTSTAT) register is set.
Debug reset is initiated when the On-Chip Debugger detects any of the following error
conditions on the DBG pin:
•
•
•
When the Z8F083 is in STOP mode, the debug reset will cause a system reset. The On-
Chip Debugger block is not reset, but the rest of the chip goes through a normal system
reset. The POR bit in the reset (RSTSTAT) register is set to 1.
The reset status (RSTSTAT) register detailed in
indicates the source of the most recent Reset event, a Stop Mode Recovery event, or a
Watchdog Timer time-out event. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer control register, which is write-
only.
See descriptions below
Serial break (a minimum of nine continuous bits low)
Framing error (received STOP bit is low)
Transmit collision (OCD and host simultaneous transmission detected by the OCD)
STOP
R
6
®
WDT
R
F0830 Series device is in STOP mode and the external RESET pin
5
EXT
R
4
0
FF0H
R
3
0
Table 11
is a read-only register that
R
Z8 Encore!
2
0
Reset and Stop Mode Recovery
Reserved
Product Specification
R
1
0
®
F0830 Series
R
0
0
30
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