ST72F32AK2T6 STMicroelectronics, ST72F32AK2T6 Datasheet - Page 33
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ST72F32AK2T6
Manufacturer Part Number
ST72F32AK2T6
Description
MCU 8BIT 8KB FLASH/ROM 32-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F32AK2T6.pdf
(157 pages)
Specifications of ST72F32AK2T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3.8 V
Width
7 mm
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5610
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F32AK2T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
Note 1: Unexpected exit from HALT may occur when SPI is in slave mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
■
N°
10
11
0
1
2
3
4
5
6
7
8
9
Falling edge
Rising edge
Falling and rising edge
MCC/RTC
19). This control allows to have up to 4 fully
TIMER A
TIMER B
Source
RESET
Block
TRAP
SPI
SCI
ei0
ei1
ei2
ei3
Reset
Software interrupt
Main clock controller time base inter-
rupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Not used
Not used
Description
Not used
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Register
MCCSR
SPICSR
SCISR
TASR
TBSR
Label
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
N/A
N/A
Priority
Priority
Priority
Higher
Order
Lower
HALT
yes
from
Exit
yes
yes
yes
yes
yes
yes
no
no
no
no
1)
ACTIVE
HALT
from
Exit
yes
yes
no
no
no
no
no
no
no
no
no
FFECh-FFEDh
FFFCh-FFFDh
FFEAh-FFEBh
FFFAh-FFFBh
FFEEh-FFEFh
FFFEh-FFFFh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
ST7232A
Vector
33/157
1