EZ80F91NAA50SG Zilog, EZ80F91NAA50SG Datasheet - Page 35
EZ80F91NAA50SG
Manufacturer Part Number
EZ80F91NAA50SG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4566
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Register Map
Table 3. Register Map
PS027001-0707
Address
(hex)
Product ID
0000
0001
0002
Interrupt Priority
0010
0011
0012
0013
0014
0015
Ethernet Media Access Controller
0020
0021
0022
0023
0024
Mnemonic
ZDI_ID_L
ZDI_ID_H
ZDI_ID_REV
INT_P0
INT_P1
INT_P2
INT_P3
INT_P4
INT_P5
EMAC_TEST
EMAC_CFG1
EMAC_CFG2
EMAC_CFG3
EMAC_CFG4
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = XX). All I/O operations using 16-bit addresses within the
0000h–00FFh
not generated if the address space programmed for the I/O chip selects overlap the
0000h–00FFh
Registers at unused addresses within the
erals are not implemented. Read access to such addresses returns unpredictable values and
Write access produces no effect.
device.
range are routed to the on-chip peripherals. External I/O chip selects are
address range.
Name
eZ80 Product ID Low Byte Register
eZ80 Product ID High Byte Register
eZ80 Product ID Revision Register
Interrupt Priority Register—Byte 0
Interrupt Priority Register—Byte 1
Interrupt Priority Register—Byte 2
Interrupt Priority Register—Byte 3
Interrupt Priority Register—Byte 4
Interrupt Priority Register—Byte 5
EMAC Test Register
EMAC Configuration Register
EMAC Configuration Register
EMAC Configuration Register
EMAC Configuration Register
Table 3
0000h–00FFh
describes the register map for the eZ80F91
range assigned to on-chip periph-
Reset
(hex)
XX
08
00
00
00
00
00
00
00
00
00
37
0F
00
Product Specification
Access
eZ80F91 ASSP
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Register Map
Page
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