EZ80F91NAA50SG Zilog, EZ80F91NAA50SG Datasheet - Page 67
EZ80F91NAA50SG
Manufacturer Part Number
EZ80F91NAA50SG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4566
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 13. Vectored Interrupt Operation
PS027001-0707
Memory
Mode
Z80 Mode
ADL Mode
Z80 Mode
ADL
Bit
0
1
0
boundary. Setting the LSB of the I register produces no effect on the interrupt vector
address.
MADL
Bit
0
0
1
bus, IVECT [8:0], by the interrupting peripheral.
IEF1
IEF2
The Starting Program Counter is effective {MBASE, PC[15:0]}.
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.
The ADL mode bit remains cleared to 0.
The interrupt vector address is located at { MBASE, I[7:1], IVECT[8:0] }.
PC[23:0]
The interrupt service routine must end with RETI.
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
IEF1
IEF2
The Starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
The ADL mode bit remains set to 1.
The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
PC[23:0]
The interrupt service routine must end with RETI.
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT[8:0], bus by the interrupting peripheral.
•
•
• The Starting Program Counter is effective {MBASE, PC[15:0]}.
• Push the 2-byte return address, PC[15:0], onto the SPL stack.
• Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode
• Set the ADL mode bit to 1.
• The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
• PC[23:0]
• The interrupt service routine must end with RETI.L
Operation
Read the LSB of the interrupt vector placed on the internal vectored interrupt
IEF1
IEF2
(because ADL = 0).
←
←
←
←
←
←
0
0
0
0
←
←
0
0
←
( { MBASE, I[7:1], IVECT[8:0] } ).
( { I[15:1], IVECT[8:0] } ).
( { I[15:1], IVECT[8:0] } )
.
Product Specification
eZ80F91 ASSP
Interrupt Controller
59
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