C8051F829-GS Silicon Laboratories Inc, C8051F829-GS Datasheet - Page 184
C8051F829-GS
Manufacturer Part Number
C8051F829-GS
Description
IC MCU 8BIT 8KB FLASH 16SOIC
Manufacturer
Silicon Laboratories Inc
Series
C8051F82xr
Datasheet
1.C8051F800DK.pdf
(250 pages)
Specifications of C8051F829-GS
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1809-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F829-GS
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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C8051F80x-83x
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 26.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “28. Timers” on page 209.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 26.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 26.2.
Figure 26.4 shows the typical SCL generation described by Equation 26.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 26.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 26.2 shows the min-
184
Timer Source
Overflows
SCL
LOW
Equation 26.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
T
Low
SMBCS1
T
Figure 26.4. Typical SMBus SCL Generation
Table 26.1. SMBus Clock Source Selection
HighMin
0
0
1
1
Equation 26.2. Typical SMBus Bit Rate
BitRate
SMBCS0
=
T
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.0
=
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
HIGH
is typically
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