MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 22

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Company
Part Number
Manufacturer
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Price
Part Number:
MC705P6ACDWE
Manufacturer:
Freescale Semiconductor
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135
Part Number:
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Manufacturer:
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Part Number:
MC705P6ACDWE
Manufacturer:
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Quantity:
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Memory
22
$000C
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Addr.
SIOP Control Register
SIOP Status Register
Port C Data Direction
Port D Data Direction
Port A Data Direction
Port B Data Direction
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
SIOP Data Register
Register (DDRA)
Register (DDRB)
Register (DDRC)
Register (DDRD)
Register Name
Unimplemented
Unimplemented
See page 37.
See page 38.
See page 38.
See page 39.
See page 37.
See page 38.
See page 38.
See page 39.
See page 43.
See page 44.
See page 44.
(PORTA)
(PORTB)
(PORTC)
(PORTD)
Figure 2-3. I/O and Control Register Summary (Sheet 1 of 3)
(SCR)
(SDR)
(SSR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
DDRA7
DDRB7
DDRC7
SDR7
SPIF
Bit 7
PC7
PD7
PA7
PB7
0
0
0
0
0
0
0
0
= Unimplemented
DDRC6
DDRA6
DDRB6
DCOL
SDR6
SPE
PA6
PB6
PC6
6
0
0
0
0
0
0
0
0
DDRA5
DDRB5
DDRC5
DDRD5
SDR5
PA5
PB5
PC5
PD5
5
0
0
0
0
0
0
0
0
DDRC4
DDRA4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
MSTR
Unaffected by reset
SDR4
PA4
PC4
R
4
0
1
0
1
0
0
0
0
0
0
0
= Reserved
DDRA3
DDRC3
SDR3
PC3
PA3
3
0
0
0
1
0
0
0
0
0
0
0
0
DDRC2
DDRA2
SSDR2
PA2
PC2
2
0
0
0
1
0
0
0
0
0
0
0
0
Freescale Semiconductor
U = Undetermined
DDRA1
DDRC1
SDR1
PC1
PA1
1
0
0
0
1
0
0
0
0
0
0
0
0
DDRC0
DDRA0
SDR0
Bit 0
PA0
PC0
0
0
0
1
0
0
0
0
0
0
0
0