MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 44
Manufacturer Part Number
IC MCU 176 BYTES RAM 28-SOIC
Specifications of MC705P6ACDWE
Number Of I /o
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
Serial Input/Output Port (SIOP)
7.3.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits.
in the register and indicates the value of each bit after reset.
SPIF — Serial Port Interface Flag
DCOL — Data Collision
7.3.3 SIOP Data Register (SDR)
This register is located at address $000C and serves as both the transmit and receive data register.
Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will destroy the previous contents. The
SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be
transmitted and/or received.
affected by reset.
SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer
has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If the SPIF is cleared before the
last rising edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of
the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL
bit will be set again. Reset clears the DCOL bit.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Figure 7-5. Serial Port Data Register (SDR)
Figure 7-4. SIOP Status Register (SSR)
shows the position of each bit in the register. This register is not
Unaffected by reset
shows the position of each bit